Waveform for D0 at the FPGA pin, with Slew = FAST and Drive = 4mA. Then run a reflection analysis on D0 again and note that there is now some ringing on this signal (Figure 3).įigure 3. Ensure that the FPGA pin is still set to be the output pin on the net ( Bi/Out).Display the Signal Integrity panel again (you can click the button down the bottom of the workspace if you closed the panel), and click the Reanalyze Design button.The associated constraint file will be updated with the new setting and opened as the active document. Click OK and then execute the subsequent engineering change order that is generated. Locate the signal D0 in the FPGA Signal Manager dialog and set the Slew Rate to the FAST option.Waveform for D0 at the FPGA pin, with Slew = SLOW and Drive = 4mA. The resulting waveform will appear, as shown in Figure 2.įigure 2. Click the Reflections button at the bottom of the panel to run a Reflection Analysis on the net D0.Set the FPGA pin to Bi/Out and the rest of the pins in the net to Bi/In. The reason for this is that we want the FPGA pin to be driving the net for the signal integrity analysis.įigure 1. To change this, right click on each pin that needs to be changed, and choose Toggle In/Out to change the status. Make sure that the direction of the FPGA pin on this net is set to Bi/Out, and that all other pins are set to Bi/In.Locate the net D0, and click the Take Over button at the top of the panel to add D0 to the right hand section of the panel.Access this dialog by clicking on the Menu button and choosing the Set Tolerances command. These are configured in the Set Screening Analysis Tolerances dialog. For Overshoot and Undershoot conditions, the Signal Integrity engine has built-in thresholds that it can test against. Note that a number of nets have a status of Not Analyzed, typically this is because these nets include a connector pin.Īs part of the screening analysis results, you will see that failed nets have red backgrounds to their cells. To analyze a net in more detail it is taken over to the right hand side of the panel, where a reflection or cross talk analysis can be performed.
Screening is used to quickly identify potential problem nets, which can then be analyzed in more detail. What has happened is that a fast analysis has been performed on all nets in the design, called a screening analysis, with the results being listed down the left side of the Signal Integrity panel. The design will be analyzed and the Signal Integrity panel will open, listing all the nets in the design.
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